With the embedded avionics industry’s inevitable move towards the use of multicore processors for new projects, it is more important than ever to understand the certification landscape for multicore avionics systems. Increased adoption of multicore processors by the embedded avionics industry is being driven by ever-increasing demands for software functionality, improved SWaP (size, weight and power) characteristics, and increasing challenges in sourcing high-performance single-core processors. While using multicore processors for embedded avionics offers many benefits, doing so in DO-178C or ED-12C projects requires meeting the additional objectives of AC 20-193 (released January 2024; for DO-178C projects) or AMC 20-193 (released January 2022; for ED-12C projects). Much of the challenge in meeting A(M)C 20-193 objectives hinges on understanding and mitigating multicore interference and providing evidence that the timing deadlines of hosted applications will always be met.

In this paper, we do a deep dive on identifying interference channels, mitigation of interference and verification of mitigations as required to meet A(M)C 20-193’s MCP_Resource_Usage_3 objective, and we show how Wind River and Rapita Systems solutions support this process.